The present invention relates to the field of semiconductor devices, and more particularly to a method for the fabrication of a semiconductor device and a semiconductor device fabricated using the same.
With the continuous development of semiconductor technology, the performance of integrated circuits has been improved primarily though shrinking the physical dimensions of the integrated circuit components (such as transistors) to achieve faster switching speed. Currently, due to the density of components, the semiconductor industry has moved to process technology nodes at 20 nm and below. The process for manufacturing semiconductor devices is subjected to various physical constraints.
At present, the manufacturing method for an interlayer dielectric layer disposed between polysilicon gate structures may include the following steps: With reference to FIG. 1A, a semiconductor substrate 100 is provided, one or more gate structures 101 are formed on semiconductor substrate 100, a silicon nitride etch stop layer 102 is formed on semiconductor substrate 100 and on gate structures 101, and an oxide layer 103 is deposited on silicon nitride etch stop layer 102. A first chemical mechanical polishing (CMP) process is performed on oxide layer 103 until the surface of silicon nitride etch stop layer 102 is exposed, as shown in FIG. 1B. Thereafter, a second CMP process is performed on the portion of silicon nitride etch stop layer 102 disposed on the top surface of gate structures 101, as shown in FIG. 1C. However, when the physical size of a semiconductor device is scaled down to 28 nm or below, after the two CMP processes have been carried out, silicon nitride residues may remain, dishing of the interlayer dielectric layer surface between adjacent gate structures may be present, and poor uniformity may result.
Referring to FIGS. 2A-2C and FIG. 3, the problem of manufacturing a current interlayer dielectric layer according to the prior art will be described in detail.
The fabrication process of an interlayer dielectric layer may have the following two problems. Firstly, a semiconductor substrate may have a densely populated region and a sparsely populated region. The densely populated region may include closely-packed gate structures and the sparsely populated region may include sparsely-packed (widely spaced apart) gate structures. Under a severe load, a large variation in the thickness of the silicon nitride layer in the different densely and sparsely populated regions may result. For example, as shown in FIG. 2A, a semiconductor substrate 200 may include a sparsely populated region A having widely spaced apart gate structures, a medium-populated region B having medium spaced gate structures, and a densely-populated region C having closely spaced gate structures. Gate structures 201 are formed in the respective regions A, B, and C, and a silicon nitride layer 202 is formed on gate structures 201. In addition, an interlayer dielectric layer 203 is formed on semiconductor substrate 200 and on silicon nitride layer 202. The top surface of interlayer dielectric layer 203 is uneven and exceeds the top surface of silicon nitride layer 202.
Referring to FIG. 2B, a first CMP process is carried out to remove excess of the interlayer dielectric layer that is above gate structure 201. In an embodiment, after the first CMP process has been carried out, the portion of silicon nitride 202 over the sparsely-populated region A has a thickness of about 500 Angstroms, the portion of silicon nitride 202 over the medium-populated region B has a thickness of about 200 Angstroms, and the portion of silicon nitride 202 over the densely-populated region C has a thickness of about 100 Angstroms. Thereafter, a second CMP process is carried out to remove the silicon nitride layer. The second CMP process uses a slurry having a high selectivity for the silicon nitride. The polishing endpoint of the first and second CMP processes is checked by a CMP monitoring endpoint device. Residues of the silicon nitride can be found on the sparsely populated region A after the completion of the two CMP processes.
Secondly, referring to FIG. 3, a semiconductor substrate 300 may include surface regions of different morphologies. For example, semiconductor substrate 300 may include a shallow trench isolation (STI) structure 301, and a polysilicon gate layer 302 may be formed on shallow trench isolation (STI) structure 301. Because STI structure 301 has a step height, polysilicon gate layer 302 may have a relatively large thickness in the vicinity of the STI structure. Due to the fact that the polysilicon gate layer is required to have the same thickness, the semiconductor substrate may have an uneven surface. When a silicon nitride etch stop layer 303 is deposited, the portion of the silicon nitride etch stop layer on gate structure 302 disposed in the vicinity of STI 301 has a larger thickness (e.g., 200 Angstroms), and the portion of the silicon nitride etch stop layer on gate structure 302 disposed away from STI 301 has a smaller thickness (e.g., 100 Angstroms). The dotted line 1 shows a cross-section view of the surface morphology of the interlayer dielectric layer after the first CMP process. The dotted line 2 shows a cross-section view of the surface morphology of the interlayer dielectric layer after the second CMP process. When performing the CMP process, after the portion of the silicon nitride layer in the vicinity of the STI region is completely removed, residues of the silicon nitride layer remain in the region away from the STI region (indicated as a dotted ellipse 3 in FIG. 3).
In view of the foregoing, a need exists for an improved method for manufacturing a semiconductor device and a semiconductor device manufactured by the same method that can overcome the deficiencies of the prior art.